Technical Workshop with Siemens, InnoFour and Inventas – Part 2

This time, the program focuses on improving design quality earlier in the development cycle, advanced verification techniques using UVVM and UVM, processor design in VHDL, and how AI-powered verification tools are beginning to change everyday engineering workflows.

The day concludes with an afterwork and mingle session where you can exchange experiences and connect with fellow FPGA professionals. 

You will learn:

• How to identify RTL issues before simulation and reduce debug cycles

• Practical methods for improving RTL quality and design-review effectiveness

• Advanced randomization techniques in UVVM

• How to build reusable and maintainable UVM agents

• Design principles behind building a RISC-V processor from scratch in VHDL

• How AI-assisted verification workflows can improve productivity throughout the verification process

About the sessions: 

Advanced hands-on workshop: Anticipating Bugs Before Simulation – Early RTL Issue Detection in Practice

Delivered by Siemens DVT Field Application Engineer Faïçal Chtourou, this advanced hands-on workshop focuses on finding potential design issues before they become simulation problems.

Participants will work through practical exercises aimed at detecting coding-quality issues, structural design problems, connectivity mistakes, clock and reset concerns, and implementation-intent mismatches. The goal is to improve RTL readiness, shorten debug cycles, and make design reviews more structured and efficient.

Participants should bring their own laptops. All required tools and lab environments will be provided onsite.

Our co-host InnoFour specializes in FPGA and ASIC development tools, with a strong focus on verification methodologies and efficient design flows, like Questa.

Advanced Randomization with UVVM – Smarter Stimulus for VHDL Verification

Marius Elvegård, Senior FPGA Developer & Discipline leader Digital at Inventas, will demonstrate advanced randomization concepts in UVVM and how structured random stimulus can improve verification quality.

The session covers techniques such as value-range control, exclusions, weighting, corner-case targeting, and methods for maintaining readable and maintainable test environments while improving verification coverage.

Building Reusable UVM Agents 

Sverre Vigander, Prinsipal FPGA developer and engineer at Inventas, will provide a practical introduction to reusable UVM agents and their role in modern verification environments.

The presentation explores agent architecture, interaction between components, and strategies for creating modular and scalable verification infrastructures that can be reused across projects.

Building a RISC-V Processor from Scratch

Yngve Hafting, Lecturer at the Research Group for Robotics and Intelligent Systems at the University of Oslo will present a small RISC-V processor developed entirely in VHDL.

The session focuses on implementation choices, clean RTL design principles, and how complete control over the RTL enables optimization, custom instructions, and application-specific processor architectures.

Agentic AI in Questa One – A New Approach to Verification Productivity 

The final session introduces Siemens' latest AI-powered verification platform, Questa One.

Participants will learn how agentic AI can assist with tasks such as RTL creation, verification planning, analysis, debugging, and closure by leveraging design context, simulation results, logs, assertions, and verification intent. Through practical examples, the session explores how AI-assisted workflows can support engineers while keeping human review and decision-making firmly in control.