Technical Workshop with Siemens, InnoFour and Inventas

Through these sessions with presentations and a hands-on workshop, we will focus on practical application, giving you tools and techniques you can take directly into your own projects. This afternoon is also a great opportunity to exchange experiences with others working in FPGA-development across industries.

You will learn:

• Efficient simulation flows using the Questa environment

• How to structure and streamline build-and-run processes

• Advanced debugging techniques using Visualizer

• Performance analysis and bottleneck identification

• Coverage analysis and verification closure

• Practical approaches to structured testbench development using UVVM

• How to automate regression testing workflows

About the sessions: 

Hands-on workshop: Questa Simulator Hidden Gems & Advanced Debugging with Visualizer

This session provides a practical overview of advanced capabilities in the Questa simulation environment. Participants will work with QIS two‑step and three‑step flows and learn how to streamline build‑and‑run processes using the qrun utility. The workshop then focuses on advanced debugging techniques with Visualizer, followed by performance analysis using the Profiler to identify and resolve simulation bottlenecks. Finally, we will cover coverage review and closure methods to complete the verification workflow. Participants should bring their own laptops; all required tools and lab environments will be provided onsite.

The workshop is runned by Faïçal Chtourou, DVT Field Application Engineer at Siemens EDA. Siemens provides industry-leading simulation and verification solutions through the Questa platform, widely used for complex digital designs. Our co-host InnoFour specializes in FPGA and ASIC development tools, with a strong focus on verification methodologies and efficient design flows, like Questa.

Presentation: Simple and Efficient FPGA Verification with UVVM and HDLRegression

Marius Elvegård, Senior FPGA Developer & Discipline leader Digital at Inventas will present a practical approach to building structured and scalable verification environments. Inventas is a leading Norwegian product development company, with good expertise in FPGA-development, embedded systems, and system design across industries.

This session demonstrates how to create a UVVM-based test-bench step-by-step, and how HDLRegression can be used to automate simulation and regression workflows. The focus is on simplicity, scalability, and efficiency, helping you reduce manual work and increase confidence in your designs.

Guest lecture: Starting on the right foot with cocotb

Yngve Hafting, Lecturer at the Research Group for Robotics and Intelligent Systems at the University of Oslo will give a practical introduction to working with cocotb. The session focuses on how cocotb manages timing and the event queue, illustrated with concrete code examples. You will also learn key principles that ensure predictable behavior in both stimulus generation and checker algorithms.