FPGA and ASIC development

When developing extremely specialized systems that will perform the most demanding tasks or operate in some of the most inhospitable regions of the universe, an FPGA can become part of the solution.

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Development of highly specialized systems for demanding tasks in inhospitable areas

Inventas has the leading independent design environment for FPGA (Field-Programmable Gate Array) in Norway. We have developed our own development methodology (UVVM) that is internationally recognized, and provides both high efficiency and quality of development. Inventas designs with all the leading technologies available for FPGA.

The development of FPGA solutions is a complex exercise in which electronic circuits are described in their own languages that are made for this purpose. Therefore, detailed knowledge of digital design is required in most applications. On the team at Inventas, we have over 25 years of experience in the field and we will be your perfect partner in all development phases.

Våre utviklere

Inventas has extensive experience in FPGA and ASIC development, and we specialize in excellent design methodology and verification with UVVM (Universal VHDL Verification Methodology). We assist in planning and implementing designs, verifying that the design is in line with specifications, and ensuring that it meets the necessary timing requirements (timing closure).

Our developers focus on specialization and application of efficient methodology and also benefit from being multidisciplinary. Many of our employees have a background in electronics, which strengthens our system understanding and ability to integrate closely with electronic components.

What we work on

Inventas has worked with applications where FPGAs and ASICs are part of the solution. Our proprietary and internationally recognized verification methodology (UVVM) ensures high quality and quality of the verification process.

When we design, we use all the leading technologies available for FPGAs. We provide assistance with everything from simple troubleshooting and support in small projects to comprehensive assignments in larger projects.

The clients we work with come from a variety of sectors, including startups, medtech, subsea and aerospace.

Depending on the project requirements and the client's needs, we undertake both design and verification tasks. Our team works closely with each client from start to finish to ensure the solutions are of the highest quality.

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We contribute

Inventas adapts its engagement based on the scope of the project and the customer's needs. We have extensive experience in all phases of the development process, and work with short assignments for sparring or debug assistance, to larger projects where we assemble a team that is responsible for design, implementation, verification and backend.

Flexible project support

We adapt to both small and large projects and offer flexible delivery models, whether work is required onsite or remote.

Complete FPGA/ASIC development

Inventas covers all development phases from concept and specification, system design and module specification, to the choice of architecture and technology.

Design and implementation

We perform extensive design work using VHDL, Verilog/SystemVerilog, and development including synthesis, place & route (P&R) and implementation with specialized FPGA tools, as well as modernization of legacy code to update and improve existing systems.

Testing and verification

We offer advanced verification and testing using UVVM and UVM. UVVM and HDLRegression, both developed by Inventas, are central to our verification processes. We develop comprehensive test plans and set up efficient test benches. HDLRegression is used for automated simulation of test benches, integrated into a CI system, to ensure that the design works as expected. In addition, we perform hardware testing and system startup.

Support and optimization

Our skilled professionals act as sparring partners and offer design reviews, debug assistance, and support through script development and backend processes.

Training and development support

We offer training in FPGA/ASIC development, with a specific focus on tools and methodologies such as UVVM and HDLRegression, to strengthen customers' technical expertise.

UVVM and HDLRegression

Inventas develops UVVM (Universal VHDL Verification Methodology), which we have posted as an open and free test framework and methodology on GitHub and IEEE SAO GitLab. All FPGA and ASIC developers at Inventas are involved in developing UVVM and are experts in good design and verification methodology.

In 2021, Inventas opened UVVM up even more to the user community and established a steering group where Inventas has one of the seats. The goal is to invite more companies to drive the development of UVVM. UVVM is supported by the European Space Agency ESA to further develop the methodology and expand its functionality.

HDLRegression is developed by Inventas with support from ESA and is a tool for structured and automated execution of VHDL and Verilog test benches for FPGA design. This tool automates the organization of files and tests, promotes advanced test structure, and integrates software development methods such as continuous integration and unit tests.

UVVM and HDLRegression are just two of the tools that Inventas uses to streamline and maintain the highest quality in our FPGA design projects.

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